The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9727342 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 08, 2017

Filed:

Dec. 11, 2014
Applicants:

Koushik Chakraborty, Logan, UT (US);

Sanghamitra Roy, Logan, UT (US);

HU Chen, Logan, UT (US);

Inventors:

Koushik Chakraborty, Logan, UT (US);

Sanghamitra Roy, Logan, UT (US);

Hu Chen, Logan, UT (US);

Assignee:

Utah State University, Logan, UT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 9/38 (2006.01); G06F 1/08 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3861 (2013.01); G06F 1/08 (2013.01); G06F 9/3869 (2013.01); G06F 11/076 (2013.01); G06F 11/0721 (2013.01);
Abstract

For an error resilient pipeline, a Dynamically Adaptable Resilient Pipeline (DARP) controller determines a minimum error pipeline stage of a processor instruction pipeline with a minimum number of errors. In addition, the DARP controller determines a maximum error pipeline stage of the instruction pipeline with a maximum number of errors. The DARP controller increases a clock frequency for the instruction pipeline if the minimum number of errors of the minimum error pipeline stage is zero and the maximum number of errors of the maximum error pipeline stage does not exceed an error threshold. In addition, the DARP controller decreases the clock frequency if the minimum number of errors exceeds an error constant.


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