The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2017
Filed:
Sep. 22, 2014
Ming-chieh Huang, San Jose, CA (US);
Chan-hong Chern, Palo Alto, CA (US);
Tao Wen Chung, San Jose, CA (US);
Yuwen Swei, Fremont, CA (US);
Chih-chang Lin, San Jose, CA (US);
Tsung-ching Huang, San Jose, CA (US);
Ming-Chieh Huang, San Jose, CA (US);
Chan-Hong Chern, Palo Alto, CA (US);
Tao Wen Chung, San Jose, CA (US);
Yuwen Swei, Fremont, CA (US);
Chih-Chang Lin, San Jose, CA (US);
Tsung-Ching Huang, San Jose, CA (US);
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.