The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Jul. 01, 2015
Applicant:

SK Hynix Inc., Icheon-Si, KR;

Inventors:

Ki-Seon Park, Icheon-si, KR;

Bo-Mi Lee, Icheon-Si, KR;

Won-Joon Choi, Icheon-Si, KR;

Guk-Cheon Kim, Icheon-Si, KR;

Assignee:

SK hynix Inc., Icheon-Si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); H01L 43/08 (2006.01); H01L 43/02 (2006.01); H01L 43/12 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
H01L 43/08 (2013.01); G06F 1/3275 (2013.01); H01L 43/02 (2013.01); H01L 43/12 (2013.01);
Abstract

This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a hole; a conductive pattern filled in the hole and having a top surface located at a level substantially same as a top surface of the interlayer dielectric layer; and an MTJ (Magnetic Tunnel Junction) structure formed over the conductive pattern to be coupled to the conductive pattern and including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein an upper portion of the conductive pattern includes a first amorphous region.


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