The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Mar. 04, 2014
Applicant:

Maxim Integrated Products, Inc., San Jose, CA (US);

Inventors:

Viren Khandekar, Flower Mound, TX (US);

Karthik Thambidurai, Plano, TX (US);

Vivek S. Sridharan, Lewisville, TX (US);

Assignee:

MAXIM INTEGRATED PRODUCTS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 23/3114 (2013.01); H01L 23/49816 (2013.01); H01L 23/562 (2013.01); H01L 24/16 (2013.01); H01L 2224/03828 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/05026 (2013.01); H01L 2224/0558 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/119 (2013.01); H01L 2224/1134 (2013.01); H01L 2224/11334 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/136 (2013.01); H01L 2224/1319 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13561 (2013.01); H01L 2224/13582 (2013.01); H01L 2224/13583 (2013.01); H01L 2224/13647 (2013.01); H01L 2224/13655 (2013.01); H01L 2224/14131 (2013.01); H01L 2224/14179 (2013.01); H01L 2224/14505 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/94 (2013.01);
Abstract

Semiconductor devices are described that have bump assemblies configured to furnish shock absorber functionality. In an implementation, a wafer-levelchip-scale package devices include an integrated circuit chip having an array of bump assemblies disposed over the integrated circuit chip. The array of bump assemblies comprises a plurality of first bump assemblies that include solder bumps composed at least substantially of a solder composition (i.e., solder bumps that do not include a core). The array further comprises a plurality of second bump assemblies that includes a solder bump having a core configured to furnish shock absorber functionality to the integrated circuit chip.


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