The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

May. 31, 2016
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Keiju Yamada, Kanagawa-ken, JP;

Takashi Yamazaki, Kanagawa-ken, JP;

Masatoshi Fukuda, Kanagawa-ken, JP;

Yasuhiro Koshio, Kanagawa-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/552 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 23/3114 (2013.01); H01L 23/3128 (2013.01); H01L 23/49805 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/544 (2013.01); H01L 24/97 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2223/54433 (2013.01); H01L 2223/54486 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/97 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/3025 (2013.01);
Abstract

According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.


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