The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Nov. 30, 2016
Applicant:

J-devices Corporation, Usuki, Oita, JP;

Inventor:

Naoki Hayashi, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/28 (2006.01); H01L 21/48 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/6835 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 24/06 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68386 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/215 (2013.01); H01L 2924/01029 (2013.01);
Abstract

Provided is a bonding method to construct a bonding with high thermal reliability between electrodes formed on both chip surfaces of a semiconductor device and wiring. The bonding method includes: bonding a semiconductor chip over a first substrate with a bonding film interposed therebetween; forming a first insulating film over the semiconductor chip; forming a first via in the first insulating film; forming a first wiring over the first insulating film so as to be electrically connected to the semiconductor chip through the first via; forming a second via in the bonding film; and forming a second wiring under the semiconductor chip so as to be electrically connected to the semiconductor chip through the second via.


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Hayashi, Naoki. (2017). Semiconductor package and its manufacturing method (U.S. Patent No. 9721900). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9721900

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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