The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Jan. 30, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

MD Altaf Hossain, Portland, OR (US);

Scott A. Gilbert, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 7/00 (2006.01); H01L 21/02 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 49/02 (2006.01); H01L 25/065 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H01L 23/522 (2006.01); H01L 21/48 (2006.01); H01L 23/538 (2006.01); H04M 1/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/49894 (2013.01); H01L 23/5222 (2013.01); H01L 23/5389 (2013.01); H01L 24/16 (2013.01); H01L 24/82 (2013.01); H01L 25/0657 (2013.01); H01L 28/40 (2013.01); H05K 1/111 (2013.01); H05K 1/181 (2013.01); H01L 2224/16227 (2013.01); H01L 2225/06572 (2013.01); H04M 1/0266 (2013.01); H05K 2201/09472 (2013.01); H05K 2201/10378 (2013.01);
Abstract

A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.


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