The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2017
Filed:
Nov. 04, 2016
Applicant:
Infineon Technologies Americas Corp., El Segundo, CA (US);
Inventor:
Michael A. Briere, Scottsdale, AZ (US);
Assignee:
Infineon Technologies Americas Corp., El Segundo, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/02 (2006.01); H01L 29/20 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0254 (2013.01); H01L 21/02002 (2013.01); H01L 21/0242 (2013.01); H01L 21/02373 (2013.01); H01L 21/02378 (2013.01); H01L 21/02381 (2013.01); H01L 21/02422 (2013.01); H01L 21/02538 (2013.01); H01L 21/30604 (2013.01); H01L 21/78 (2013.01); H01L 23/562 (2013.01); H01L 29/2003 (2013.01); H01L 2924/0002 (2013.01);
Abstract
According to an embodiment of a method of fabricating III-Nitride semiconductor dies, the method includes: growing a III-Nitride body over a group IV substrate in a semiconductor wafer; forming at least one device layer over the III-Nitride body; etching grid array trenches in the III-Nitride body and in the group IV substrate; forming an edge trench around a perimeter of the semiconductor wafer, the grid array trenches terminating inside the group IV substrate; and forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.