The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Jul. 07, 2014
Applicants:

Didier Salle, Toulouse, FR;

Olivier Doare, La Salvetat St Gilles, FR;

Christophe Landez, Toulouse, FR;

Inventors:

Didier Salle, Toulouse, FR;

Olivier Doare, La Salvetat St Gilles, FR;

Christophe Landez, Toulouse, FR;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01S 7/40 (2006.01); G01S 13/02 (2006.01); G01S 7/03 (2006.01); G01S 13/34 (2006.01); H03C 3/09 (2006.01); G01S 13/58 (2006.01); G01S 13/93 (2006.01);
U.S. Cl.
CPC ...
G01S 7/4008 (2013.01); G01S 7/032 (2013.01); G01S 13/02 (2013.01); G01S 13/343 (2013.01); H03C 3/0925 (2013.01); G01S 13/584 (2013.01); G01S 13/931 (2013.01);
Abstract

A circuitry for and a method of generating a frequency modulated radar transmitter signal are provided. The circuitry comprises a modulation signal generator for generating a modulation signal having a waveform describing a required frequency modulation of the frequency modulated radar transmitter signal and comprises a PLL circuitry for generating the frequency modulated radar transmitter signal in dependence of the modulation signal. In the PLL circuitry a controllable frequency divider controls the output frequency of the PLL circuitry in dependence of the modulation signal. The PLL circuitry further comprises a phase detector, a controllable oscillator and possibly a low pass filter. The PLL circuitry further comprises a calibration circuitry being configured to control a parameter of at least one of the phase detector and the controllable oscillator to maintain a loop gain of PLL circuitry.


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