The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2017
Filed:
Feb. 19, 2015
Applicant:
Peregrine Semiconductor Corporation, San Diego, CA (US);
Inventors:
Poojan Wagh, Sleepy Hollow, IL (US);
Joseph Golat, Cary, IL (US);
David Kovac, Arlington Heights, IL (US);
Jeffrey A. Dykstra, Woodstock, IL (US);
Chris Olson, Palatine, IL (US);
Assignee:
Peregrine Semiconductor Corporation, San Diego, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H03G 3/20 (2006.01); H03F 3/21 (2006.01); H03F 1/02 (2006.01); H03F 1/22 (2006.01); H03F 1/32 (2006.01); H03F 1/56 (2006.01); H03F 3/195 (2006.01); H03F 3/24 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
H03F 3/211 (2013.01); H03F 1/025 (2013.01); H03F 1/0227 (2013.01); H03F 1/0244 (2013.01); H03F 1/0277 (2013.01); H03F 1/223 (2013.01); H03F 1/3247 (2013.01); H03F 1/3282 (2013.01); H03F 1/56 (2013.01); H03F 3/195 (2013.01); H03F 3/24 (2013.01); H03F 3/45183 (2013.01); H03F 3/45188 (2013.01); H03F 2200/102 (2013.01); H03F 2200/108 (2013.01); H03F 2200/15 (2013.01); H03F 2200/18 (2013.01); H03F 2200/222 (2013.01); H03F 2200/336 (2013.01); H03F 2200/387 (2013.01); H03F 2200/408 (2013.01); H03F 2200/411 (2013.01); H03F 2200/451 (2013.01); H03F 2200/534 (2013.01); H03F 2200/537 (2013.01); H03F 2200/541 (2013.01); H03F 2200/61 (2013.01); H03F 2200/78 (2013.01); H03F 2201/3233 (2013.01); H03F 2203/21127 (2013.01); H03F 2203/45366 (2013.01); H03F 2203/45544 (2013.01); H03F 2203/45638 (2013.01); H03F 2203/45731 (2013.01);
Abstract
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented.