The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2017

Filed:

Feb. 08, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Szu-Ying Chen, Toufen Township, TW;

Meng-Hsun Wan, Taipei, TW;

Dun-Nian Yaung, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 25/50 (2013.01); H01L 2224/033 (2013.01); H01L 2224/03019 (2013.01); H01L 2224/0384 (2013.01); H01L 2224/03848 (2013.01); H01L 2224/04105 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01074 (2013.01);
Abstract

A device comprises a first chip comprising a plurality of first interconnect structures over a first substrate, a plurality of first connection pads over the plurality of first interconnect structures and a plurality of first bonding pads, wherein a first bonding pad is formed over a corresponding first connection pad, and a second chip comprising a plurality of second interconnect structures over a second substrate and a plurality of second bonding pads over the plurality of second interconnect structures, wherein the first chip and the second chip are face-to-face bonded together, and wherein a first bonding pad is in direct contact with a corresponding second bonding pad.


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