The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Dec. 01, 2015
Applicant:

Stmicroelectronics SA, Montrouge, FR;

Inventors:

Lionel Vogt, La Rochette, FR;

Baudouin Martineau, Tencin, FR;

Aurelien Larie, Sabres, FR;

Assignee:

STMicroelectronics SA, Montrouge, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 1/02 (2006.01); H03F 3/193 (2006.01); H03F 3/21 (2006.01); H03F 3/195 (2006.01); H03F 3/24 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0205 (2013.01); H03F 1/0261 (2013.01); H03F 3/193 (2013.01); H03F 3/195 (2013.01); H03F 3/211 (2013.01); H03F 3/245 (2013.01); H03F 3/45179 (2013.01); H03F 2200/432 (2013.01); H03F 2200/451 (2013.01); H03F 2200/516 (2013.01); H03F 2203/21106 (2013.01); H03F 2203/45394 (2013.01);
Abstract

An amplifier includes at least two amplification stages coupled in parallel. Each amplification stage includes at differential pair of amplifying MOS transistors having gates connected to a first and second input nodes common to amplifying stages, and bulk regions connected to each other but insulated from bulk regions of the amplifying MOS transistors of the other amplification stages. A configuration circuit generates bias voltage for application to the bulk terminals in each amplification stage to set the threshold voltages of the amplifying MOS transistors, and thus configuring the operating range of each amplification stage so that different amplification stages have different operating ranges.


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