The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Mar. 31, 2014
Applicant:

Edge Electrons Limited, Hong Kong, HK;

Inventor:

Neal George Stewart, Hong Kong, HK;

Assignee:

Edge Electrons Limited, Hong Kong, HK;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 1/42 (2007.01); H02J 3/18 (2006.01); G01R 21/00 (2006.01); G01R 21/06 (2006.01); G01R 23/02 (2006.01);
U.S. Cl.
CPC ...
H02M 1/4266 (2013.01); G01R 21/003 (2013.01); G01R 21/006 (2013.01); G01R 21/06 (2013.01); G01R 23/02 (2013.01); H02J 3/1828 (2013.01); Y02E 40/30 (2013.01);
Abstract

A computer-implementable control algorithm that measures: 1) the reactive power; 2) the power factor; 3) the voltage; and 4) the line frequency. The algorithm calculates the differential compensation capacitance required that is either positive (capacitance to be added), or negative (capacitance to be removed). The new compensation capacitance is calculated from the sum or difference of the differential compensation capacitance and the current compensation capacitance. The algorithm compares the capacitor switching bit pattern for the current compensation capacitance and the capacitor switching bit pattern for the new compensation capacitance, and selects a capacitor switching bit map accordingly. The capacitor switch combination for the new compensation capacitance is switched in incrementally according to the capacitor switching bit map. To reach the selected capacitor switch combination, only one switch is switched at a time to minimize the line transient noise. This part of the algorithm continues to run until the PF is corrected, with the capacitor switches being switched on/off each delayed by a millisecond interval to minimize line transient noise.


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