The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Dec. 23, 2014
Applicant:

Northrop Grumman Systems Corporation, Falls Church, VA (US);

Inventors:

Eric J. Stewart, Silver Spring, MD (US);

Bettina A. Nechay, Annapolis, MD (US);

Karen M. Renaldo, Pasadena, MD (US);

Howell G. Henry, Ellicott City, MD (US);

Ronald G. Freitag, Catonsville, MD (US);

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION, Falls Church, VA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/02 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/47 (2006.01); H01L 29/778 (2006.01); H01L 29/417 (2006.01); H01L 29/812 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66477 (2013.01); H01L 29/42316 (2013.01); H01L 29/42364 (2013.01); H01L 29/475 (2013.01); H01L 29/7786 (2013.01); H01L 29/2003 (2013.01); H01L 29/41758 (2013.01); H01L 29/812 (2013.01);
Abstract

A dual-channel field effect transistor (FET) device having increased amplifier linearity and a method of manufacturing same are disclosed. In an embodiment, the device includes a channel layer having a top surface and provided within a channel between a source electrode and a drain electrode. A barrier layer is formed on the channel layer in alternating first and second barrier thicknesses along the channel. The first barrier thicknesses form thinner regions and the second barrier thicknesses form thicker regions. A gate electrode is deposited on the barrier layer. The thinner regions have a first pinch-off voltage and the thicker regions have a larger second pinch-off voltage, such that the thinner and thicker regions are configured to turn on at different points on a drain current-gate voltage transfer curve. Transfer curve linearity is increased as a function of the gate voltage.


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