The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2017
Filed:
Apr. 18, 2016
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventors:
Charaf-Eddine Souria, Toulouse, FR;
Gilles Montoriol, Plaisance du Touch, FR;
Stéphane Damien Thuries, Saubens, FR;
Assignee:
NXP USA, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 24/94 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/13014 (2013.01); H01L 2224/13026 (2013.01); H01L 2924/014 (2013.01); H01L 2924/30205 (2013.01);
Abstract
A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 GHz.