The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Sep. 09, 2013
Applicant:

Kyocera Corporation, Kyoto-shi, Kyoto, JP;

Inventors:

Masanobu Kitada, Kyoto, JP;

Hideki Matsushita, Kyoto, JP;

Assignee:

KYOCERA CORPORATION, Kyoto-Shi, Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/36 (2006.01); H01L 21/308 (2006.01); H01L 21/86 (2006.01); H01L 21/263 (2006.01); H01L 21/762 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/36 (2006.01); H01L 21/20 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/86 (2013.01); H01L 21/02002 (2013.01); H01L 21/20 (2013.01); H01L 21/2007 (2013.01); H01L 21/263 (2013.01); H01L 21/76251 (2013.01); H01L 29/04 (2013.01); H01L 29/0649 (2013.01); H01L 29/16 (2013.01); H01L 29/36 (2013.01);
Abstract

Provided is a composite substrate which has a high-performance semiconductor layer. A composite substrate of the present invention comprises: a supporting substrate which is formed of an insulating material; a semiconductor layer which is formed of a single crystal semiconductor that is superposed on and joined to the supporting substrate; and interfacial inclusions which are present in the interface between the supporting substrate and the semiconductor layer at a density of 10atoms/cmor less, and which are formed of a metal element that is different from the constituent elements of the supporting substrate and the semiconductor layer.


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