The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Jun. 24, 2015
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Kalpeshkumar Girishchandra Dave, Bangalore, IN;

Naveen Chandra Srivastava, Kanpur, IN;

Pankaj Kumar, Hardoi, IN;

Janardhan Achanta, Kakinada, IN;

Shreekanth Karandoor Sampigethaya, Kannamangala, IN;

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); G03F 7/00 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); H01L 21/28123 (2013.01); G03F 7/0002 (2013.01); G06F 17/5081 (2013.01); H01L 21/823425 (2013.01);
Abstract

Systems, apparatuses, and methods for reducing the area of a semiconductor structure. A spacing violation may be detected for a gap width used to separate first and second regions of a layer of semiconductor material. In response to detecting the violation, the first and second regions are merged into a combined region, and then a cut mask layer is formed above the combined region. Next, an etch process is performed through the cut mask layer to remove an exposed third region within the combined region, wherein the exposed third region is interposed between first and second region portions of the combined region.


Find Patent Forward Citations

Loading…