The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Aug. 05, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Ming Ho, Hsinchu, TW;

Ke-Ying Su, Taipei, TW;

Hsien-Hsin Sean Lee, Duluth, GA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G03F 1/00 (2012.01); G21K 5/00 (2006.01); G03F 1/70 (2012.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G03F 1/70 (2013.01); G06F 17/5081 (2013.01); G06F 2217/12 (2013.01); G21K 5/00 (2013.01);
Abstract

A method of includes determining a first set of width bias values of an i-th set of layout patterns of an original layout according a first type width variation. The original layout has N sets of layout patterns corresponding to N masks, where the i-th set of layout patterns has an i-th mask assignment corresponding to an i-th mask of the N masks. The order index i is an integer from 1 to N, and N is an integer and greater than 1. A second set of width bias values of the i-th set of layout patterns of the original layout is determined according to a second type width variation. The modified layout is generated based on the first and second sets of width bias values of the i-th set of layout patterns.


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