The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2017
Filed:
Mar. 10, 2015
Method and apparatus for memory aliasing detection in an out-of-order instruction execution platform
Intel Corporation, Santa Clara, CA (US);
Oleg Margulis, Los Gatos, CA (US);
Sumit Ahuja, Mountain View, CA (US);
Polychronis Xekalakis, San Jose, CA (US);
Yongjun Park, Santa Clara, CA (US);
Vineeth Mekkat, San Jose, CA (US);
Igor Yanover, Yokneam Illit, IL;
Sebastian Winkel, Los Altos, CA (US);
Ethan Schuchman, Santa Clara, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and write operations in a program order and to responsively reorder the read and write operations; adjustment information attachment logic to associate adjustment information with one or more of the set of read and write operations, wherein for a read operation the adjustment information is to indicate a number of write operations which the read operation has bypassed and for a write operation the adjustment information is to indicate a number of read operations which have bypassed the write operation; and out-of-order processing logic to determine whether execution of the reordered read and write operations will result in a conflict based, at least in part, on the adjustment information associated with the one or more reads and writes.