The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Aug. 29, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ren Wang, Portland, OR (US);

Kevin B. Theobald, Hillsboro, OR (US);

Zeshan A. Chishti, Hillsboro, OR (US);

Zhaojuan Bian, Shanghai, CN;

Aamer Jaleel, Northborough, MA (US);

Tsung-Yuan C. Tai, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/18 (2006.01); G06F 12/0811 (2016.01); G06F 12/0895 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 12/0895 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/601 (2013.01); Y02B 60/1225 (2013.01);
Abstract

Systems and methods for managing shared cache by multi-core processor. An example processing system comprises: a plurality of processing cores, each processing core communicatively coupled to a last level cache (LLC) slice; and a cache control logic coupled to the plurality of processing cores, the cache control logic configured to perform one of: making an LLC slice of an inactive processing core available to an active processing core or power gating the LLC slice, based on estimating cache requirements by active processing cores.


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