The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Sep. 26, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nalini Vasudevan, Sunnyvale, CA (US);

Cheng Wang, San Ramon, CA (US);

Youfeng Wu, Palo Alto, CA (US);

Albert Hartono, Santa Clara, CA (US);

Sara S. Baghsorkhi, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/312 (2006.01); G06F 9/38 (2006.01); G06F 15/76 (2006.01); G06F 9/30 (2006.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3842 (2013.01); G06F 9/3004 (2013.01); G06F 9/3013 (2013.01); G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30043 (2013.01); G06F 9/30174 (2013.01); G06F 9/3824 (2013.01); G06F 9/3834 (2013.01); G06F 9/3838 (2013.01); G06F 15/8053 (2013.01);
Abstract

An apparatus and method for speculative vectorization. For example, one embodiment of a processor comprises: a queue comprising a set of locations for storing addresses associated with vectorized memory access instructions; and execution logic to execute a first vectorized memory access instruction to access the queue and to compare a new address associated with the first vectorized memory access instruction with existing addresses stored within a specified range of locations within the queue to detect whether a conflict exists, the existing addresses having been previously stored responsive to one or more prior vectorized memory access instructions.


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