The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Feb. 28, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Israel Diamand, Aderet, IL;

Asaf Rubinstein, Tel-Aviv, IL;

Arik Gihon, Rishon Le Zion, IL;

Tal Kuzi, Tel Aviv, IL;

Tomer Ziv, Rishon Lezion, IL;

Nadav Shulman, Tel Mond, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 1/324 (2013.01); G06F 1/3228 (2013.01); G06F 1/26 (2013.01);
Abstract

In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.


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