The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Aug. 05, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rainer W Bachl, Nuremberg, DE;

Vinay V Nair, Nuremberg, DE;

Michael A Ruder, Pommelsbrunn, DE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/10 (2006.01); H04L 27/01 (2006.01); H04L 5/00 (2006.01); H04B 7/04 (2017.01); H04W 72/04 (2009.01); H04J 11/00 (2006.01); H04B 7/0456 (2017.01); H04W 88/08 (2009.01);
U.S. Cl.
CPC ...
H04L 27/01 (2013.01); H04B 7/04 (2013.01); H04B 7/0456 (2013.01); H04J 11/00 (2013.01); H04L 5/0007 (2013.01); H04L 5/0032 (2013.01); H04W 72/042 (2013.01); H04W 72/0453 (2013.01); H04W 88/08 (2013.01);
Abstract

A communication device is provided including a receiver to receive a signal set. A first equalizer equalizes the signal set in accordance with a first equalization process taking into account that the signal set includes an inter cell interference signal, thereby generating a first equalized signal set. A first calculating circuit is configured to calculate a predefined characteristic of the first equalized signal set. A second equalizer equalizes the signal set in accordance with a second equalization process taking into account that the signal set is free from an inter cell interference signal, thereby generating a second equalized signal set. A second calculating circuit is configured to calculate a predefined characteristic of the second equalized signal set. A selecting circuit is configured to select the first equalized signal set or the second equalized signal set for further processing based on the determined predefined characteristics.


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