The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Mar. 06, 2012
Applicants:

Hyun Jun Kim, Seoul, KR;

Hyung Kook Chung, Seoul, KR;

Hong Bae Kim, Seoul, KR;

Inventors:

Hyun Jun Kim, Seoul, KR;

Hyung Kook Chung, Seoul, KR;

Hong Bae Kim, Seoul, KR;

Assignee:

Amkor Technology, Inc., Tempe, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4842 (2013.01); H01L 21/561 (2013.01); H01L 23/3107 (2013.01); H01L 23/49548 (2013.01); H01L 24/49 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/49433 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92247 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01027 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15747 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/351 (2013.01);
Abstract

A semiconductor package or device including a uniquely configured leadframe defining a plurality of leads which are arranged and partially etched in a manner facilitating a substantial reduction in burr formation resulting from a saw singulation process used to complete the fabrication of the semiconductor device. The semiconductor device includes a die pad defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the leads being exposed in a common exterior surface of the package body.


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