The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Dec. 09, 2016
Applicant:

Microsemi Soc Corporation, San Jose, CA (US);

Inventor:

Volker Hecht, Barsinghausen, DE;

Assignee:

Microsemi SoC Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); H01L 27/24 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); H01L 23/528 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); G11C 2013/0078 (2013.01); G11C 2213/79 (2013.01);
Abstract

A pair of adjacent ReRAM cells in an array includes a first bit line for a row of the array, a second bit line for the row of the array, a p-channel word line associated with two adjacent columns in the array, and an n-channel word line associated with the two adjacent columns. A pair of ReRAM cells in the adjacent columns in the row each includes a switch node, a first ReRAM device connected between the first bit line and the source of a p-channel transistor. The drain of the p-channel transistor is connected to the switch node, and its gate is connected to the p-channel word line. A second ReRAM device is connected between the second bit line and the source of an n-channel transistor. The drain of the n-channel transistor is connected to the switch node, and its gate is connected to the n-channel word line.


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