The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Oct. 01, 2015
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Tatsuya Onuki, Kanagawa, JP;

Kiyoshi Kato, Kanagawa, JP;

Wataru Uesugi, Kanagawa, JP;

Takahiko Ishizu, Kanagawa, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/4091 (2006.01); G11C 7/02 (2006.01); G11C 11/4094 (2006.01); G11C 11/4097 (2006.01); H01L 27/108 (2006.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G11C 7/02 (2013.01); G11C 11/4094 (2013.01); G11C 11/4097 (2013.01); H01L 27/10808 (2013.01); G11C 5/025 (2013.01); G11C 2213/71 (2013.01);
Abstract

A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.


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