The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Aug. 14, 2014
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Michael J. Smith, San Francisco, CA (US);

Josh P. de Cesare, Campbell, CA (US);

Brijesh Tripathi, Los Altos, CA (US);

Derek Iwamoto, San Francisco, CA (US);

Shane J Keil, San Jose, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01); G06F 13/10 (2006.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4226 (2013.01); G06F 13/105 (2013.01); G06F 13/385 (2013.01); G06F 13/4022 (2013.01); G06F 13/4059 (2013.01);
Abstract

An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.


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