The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Mar. 15, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Oluf Bagger, Aalborg, DK;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 13/364 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/364 (2013.01); G06F 1/26 (2013.01); G06F 13/4068 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01);
Abstract

A system and method consistent with the present disclosure includes a master device, bus interface link, and slave device. The master device includes a power supply and a detection unit to detect an impedance of the power supply. The inverter provides a first path to the power supply on a first stage of a clock signal and. Further, the inverter provides a second path to a first ground line on a second stage of a clock signal. The bus interface link couples the master device to a slave device. Additionally, a bi-directional communications line is coupled to the bus interface link. A gating component provides a second ground line to the power supply through the first path. Furthermore, a receiver determines bit values from a plurality of clock data signals transmitted from the master device.


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