The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

May. 09, 2016
Applicants:

Intel Corporation, Santa Clara, CA (US);

Duke University, Duham, NC (US);

Inventors:

Shih-Lien L. Lu, Portland, OR (US);

Helia Naeimi, Sunnyvale, CA (US);

Ralph Nathan, Durham, NC (US);

Daniel Sorin, Durham, NC (US);

Assignees:

Intel Corporation, Santa Clara, CA (US);

Duke University, Durham, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); G06F 9/30 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G06F 11/10 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/30101 (2013.01);
Abstract

A mechanism for recycling error bits in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprising a floating point unit (FPU) to generate a result value from applying an operation on floating point number inputs to the FPU and generate an error value using the result value. The FPU also writes the result value to a first register of the processing device dedicated to storing results from the operation of the FPU and writes the error value to a second register of the processing device dedicated to storing errors from the operation of the FPU. The second register is separate from the first register.


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