The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Dec. 29, 2011
Applicants:

Jonathan D. Combs, Austin, TX (US);

Jason W. Brandt, Austin, TX (US);

Benjamin C. Chaffin, Portland, OR (US);

Julio Gago, Barcelona, ES;

Inventors:

Jonathan D. Combs, Austin, TX (US);

Jason W. Brandt, Austin, TX (US);

Benjamin C. Chaffin, Portland, OR (US);

Julio Gago, Barcelona, ES;

Andrew F. Glew, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 9/38 (2006.01); G06F 12/1036 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3814 (2013.01); G06F 9/3851 (2013.01); G06F 12/1036 (2013.01);
Abstract

In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread.


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