The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

Dec. 23, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Shreyas Sen, Hillsboro, OR (US);

Ritesh Bhat, Hillsboro, OR (US);

Yanjie Wang, Hillsboro, OR (US);

Stefano Pellerano, Beaverton, OR (US);

Christopher Hull, Portland, OR (US);

Farhana Sheikh, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/10 (2006.01); H04L 27/14 (2006.01); H04W 52/02 (2009.01); H04B 1/16 (2006.01); H04W 88/06 (2009.01);
U.S. Cl.
CPC ...
H04B 1/1027 (2013.01); H04B 1/16 (2013.01); H04L 27/14 (2013.01); H04W 52/0209 (2013.01); H04W 88/06 (2013.01);
Abstract

A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein, and further configured to output a blocker detection signal indicative of the existence of the blocker. The receiver system further includes a configurable receiver circuit configured to receive the RF input signal and the blocker detection signal, and selectively configure the configurable receiver circuit between a first mode wherein the configurable receiver circuit exhibits first linearity characteristics, and a second mode wherein the configurable receiver circuit exhibits second, different linearity characteristics based on the blocker detection signal.


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