The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

Oct. 09, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Vasily Vladimirovich Korolev, Solnechnogorsk, RU;

Alexander Ivanovich Kornilov, Zelenograd, RU;

Victor Mikhailovich Mikhailov, Zelenograd, RU;

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/289 (2006.01); H03K 3/012 (2006.01); H03K 3/3562 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); H03K 3/35625 (2013.01);
Abstract

A flip-flop structure comprising a master latch and a slave latch. An output of an input stage of the master latch is coupled to the output of the master latch. The input stage is arranged to drive a logical state at the output of the master latch corresponding to a logical state of the received data input signal during a first phase of a clock signal. A feedback component is arranged to sample a logical state at the output of the master latch and to drive a logical state at the output of the master latch based on the sampled logical state at the output of the master latch such that the sampled logical state is maintained, during a second phase of the clock signal.


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