The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

Jan. 17, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Yi-Ming Huang, Tainan, TW;

Hsiu-Ting Chen, Tainan, TW;

Shih-Chieh Chang, Taipei, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 29/66628 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01); H01L 29/66636 (2013.01);
Abstract

The present disclosure provides a semiconductor structure having an insulating layer positioning on a substrate; a semiconductor fin partially located in the insulating layer; and a metal gate over the semiconductor fin and the insulating layer. The semiconductor fin includes a first region including a first lattice constant and a second region in proximity to the metal gate, including a second lattice constant. At least one dislocation is located only in the second region of the semiconductor fin. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a gate over a first semiconductor layer, removing a portion of the first semiconductor layer in proximity to a sidewall of the gate and obtaining a recess, and forming a second semiconductor layer in the recess. At least one dislocation is in-situ formed in the second semiconductor layer without extending to the first semiconductor layer.


Find Patent Forward Citations

Loading…