The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

Jul. 09, 2015
Applicant:

Crossbar, Inc., Santa Clara, CA (US);

Inventors:

Hagop Nazarian, San Jose, CA (US);

Sung Hyun Jo, Sunnyvale, CA (US);

Harry Yue Gee, Milpitas, CA (US);

Assignee:

CROSSBAR, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 29/423 (2006.01); H01L 49/02 (2006.01); H01L 45/00 (2006.01); H01L 29/66 (2006.01); G11C 13/00 (2006.01); G11C 14/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2463 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 14/00 (2013.01); G11C 14/0045 (2013.01); H01L 27/2436 (2013.01); H01L 28/60 (2013.01); H01L 29/4236 (2013.01); H01L 29/42372 (2013.01); H01L 29/66613 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/145 (2013.01); H01L 45/148 (2013.01); H01L 45/1608 (2013.01); G11C 2213/53 (2013.01); G11C 2213/79 (2013.01);
Abstract

A high density non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A deep trench MOS ('metal-oxide-semiconductor') transistor having a floating gate with small area relative to conventional devices can be provided, in addition to a capacitor or transistor acting as a capacitor. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. The small area floating gate of the deep trench transistor can be connected to the other side of the selector device, and a second transistor can be connected in series with the deep trench transistor.


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