The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

Jun. 10, 2016
Applicants:

Seung-min Lee, Suwon-si, KR;

Hoo-sung Cho, Yongin-si, KR;

Jeong-seok Nam, Osan-si, KR;

Jong-min Lee, Ulsan, KR;

Yong-joon Choi, Suwon-si, KR;

Inventors:

Seung-Min Lee, Suwon-si, KR;

Hoo-Sung Cho, Yongin-si, KR;

Jeong-Seok Nam, Osan-si, KR;

Jong-Min Lee, Ulsan, KR;

Yong-Joon Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11565 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01);
Abstract

A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.


Find Patent Forward Citations

Loading…