The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2017
Filed:
Sep. 16, 2011
Applicants:
Arifur Rahman, San Jose, CA (US);
Jon M. Long, Livermore, CA (US);
Yuanlin Xie, Fremont, CA (US);
Inventors:
Assignee:
Altera Corporation, San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/00 (2006.01); H05K 3/46 (2006.01); H05K 1/14 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/1703 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15321 (2013.01); H05K 1/141 (2013.01); H05K 3/4697 (2013.01); H05K 2201/1053 (2013.01);
Abstract
An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.
Rahman, Arifur. (2017). Apparatus for stacked electronic circuitry and associated methods (U.S. Patent No. 9698123). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9698123
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile