The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

Nov. 05, 2015
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Sundar Rajan, Palo Alto, CA (US);

Charles R. Berghorn, Staatsburg, NY (US);

Mitchell G. Poplack, San Jose, CA (US);

Assignee:

CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/455 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 9/455 (2013.01); G06F 17/5027 (2013.01); G06F 17/5054 (2013.01); G01R 31/317 (2013.01);
Abstract

A system for concurrent target diagnostics is disclosed. The system comprises dedicated FPGA for generating test data to test target connections between an emulator and a target system. In this way, domains of the emulator may continue to emulate at least a portion of a hardware design during the testing of the target connections. Further, a multiplexer operable to select target connections for testing eliminates errors resulting from manual swapping of target connections during the testing process. The system further comprises multiple paths to a target pod. The paths enable monitoring and reporting on the status of target connections between an emulator and a target system.


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