The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2017

Filed:

Mar. 25, 2015
Applicants:

Sridharan Ranganathan, San Ramon, CA (US);

Satheesh Chellappan, Folsom, CA (US);

Inventors:

Sridharan Ranganathan, San Ramon, CA (US);

Satheesh Chellappan, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4291 (2013.01); G06F 1/324 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01);
Abstract

Techniques and mechanisms to provide common interface logic for multiple protocol engines to access physical layer circuitry at different times. In an embodiment, a state machine of an interface device is to participate in exchanges with physical layer resources on behalf of any of various protocol engines coupled to the interface device via different respective interfaces. Based on state transitions by the state machine, circuitry corresponding to a particular one of such interfaces may selectively send a clock signal for operation of a port controller attempting to access the physical layer circuitry. In some embodiments, multiple interface devices are configured to provide an hierarchical interface architecture for more than two port controllers that variously support at least two protocols.


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