The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

Nov. 16, 2015
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Shuichi Toriyama, Yokohama, JP;

Reika Ichihara, Yokohama, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/145 (2013.01); G11C 13/0007 (2013.01); G11C 13/0023 (2013.01); G11C 13/0026 (2013.01); H01L 27/249 (2013.01); H01L 27/2454 (2013.01); H01L 45/08 (2013.01); H01L 45/1226 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); G11C 2213/15 (2013.01); G11C 2213/71 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes a plurality of first wirings, a plurality of second wirings, a variable resistance layer, a first barrier insulating layer, and a second barrier insulating layer. The first wirings are disposed at predetermined pitches in a first direction intersecting with a substrate. The second wirings are disposed at predetermined pitches in a second direction intersecting with the first direction. The second wirings are formed to extend in the first direction. The variable resistance layer is disposed between the first wiring and the second wiring. The variable resistance layer is disposed at a position where the first wiring intersects with the second wiring. The first barrier insulating layer is disposed between the first wiring and the variable resistance layer. The second barrier insulating layer is disposed between the second wiring and the variable resistance layer.


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