The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

Nov. 27, 2012
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Huilong Zhu, Poughkeepsie, NY (US);

Haizhou Yin, Poughkeepsie, NY (US);

Zhijiong Luo, Poughkeepsie, NY (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/308 (2006.01); H01L 21/762 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/0243 (2013.01); H01L 21/0274 (2013.01); H01L 21/02381 (2013.01); H01L 21/02433 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/02639 (2013.01); H01L 21/308 (2013.01); H01L 21/76224 (2013.01); H01L 21/823412 (2013.01); H01L 21/823425 (2013.01); H01L 21/823468 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823864 (2013.01); H01L 29/0653 (2013.01); H01L 29/0688 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/41783 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/7834 (2013.01);
Abstract

A semiconductor structure is provided, comprising a substrate (), a support structure (), a base region (), a gate stack, a spacer (), and a source/drain region, wherein the gate stack is located above the base region (), and the base region () is supported above the substrate () by the support structure (), wherein the support structure () has a sigma-shaped lateral cross-section; an isolation structure () is formed below edges on both sides of the base region (), wherein a portion of the isolation structure () is connected to the substrate (); a cavity () is formed between the isolation structure () and the support structure (); and a source/drain region is formed on both sides of the base region () and the isolation structure (). Accordingly, a method for manufacturing the semiconductor structure is also provided.


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