The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

Apr. 23, 2014
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Kuang Ting Chen, Taipei, TW;

Ching-Wei Wu, Caotun Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 3/06 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 7/18 (2006.01); H01L 27/06 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0625 (2013.01); G06F 3/0665 (2013.01); G06F 3/0689 (2013.01); G11C 5/025 (2013.01); G11C 5/063 (2013.01); G11C 5/066 (2013.01); G11C 7/1075 (2013.01); G11C 7/18 (2013.01); H01L 27/0688 (2013.01); G11C 2207/108 (2013.01); G11C 2207/2209 (2013.01); G11C 2211/4016 (2013.01); H01L 27/1104 (2013.01);
Abstract

Some embodiments of the present disclosure relate to a memory device wherein a single memory cell array is partitioned between two or more tiers which are vertically integrated on a single substrate. The memory device also includes support circuitry including a control circuit configured to read and write data to the memory cells on each tier, and a shared input/output (I/O) architecture which is connected the memory cells within each tier and configured to receive input data word prior to a write operation, and further configured to provide output data word after a read operation. Other devices and methods are also disclosed.


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