The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2017

Filed:

Apr. 28, 2016
Applicant:

Avago Technologies General Ip (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

Adesh Garg, Aliso Viejo, CA (US);

Ali Nazemi, Aliso Viejo, CA (US);

Anand Jitendra Vasani, Laguna Hills, CA (US);

Hyo Gyuem Rhew, Irvine, CA (US);

Jiawen Zhang, Irvine, CA (US);

Jun Cao, Irvine, CA (US);

Meisam Honarvar Nazari, Aliso Viejo, CA (US);

Afshin Momtaz, Laguna Hills, CA (US);

Tamer Ali, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01); H03M 1/10 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1009 (2013.01); H03M 1/10 (2013.01); H03M 1/66 (2013.01); H03M 1/662 (2013.01);
Abstract

A time-interleaved digital-to-analog converter (DAC) architecture is provided. The DAC architecture includes a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal. First and second DAC circuits receive respective first and second data streams of the plurality of data streams and selectively process the respective first and second data streams to generate a respective DAC output signal. The respective DAC output signals of the first and second DAC circuits are coupled together to provide an output signal of the DAC architecture.


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