The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2017

Filed:

Apr. 05, 2016
Applicant:

Shinko Electric Industries Co., Ltd., Nagano, JP;

Inventor:

Kazutaka Kobayashi, Nagano, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/18 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 23/13 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/42 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/13 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/296 (2013.01); H01L 23/3121 (2013.01); H01L 23/42 (2013.01); H01L 23/49894 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48235 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1531 (2013.01);
Abstract

A wiring board includes a substrate having first and second opposite surfaces, a first adhesive layer on the first surface of the substrate, a thermal diffusion metal pattern on the first adhesive layer, multiple vias vertically extending from the thermal diffusion metal pattern into the substrate through the first adhesive layer with a gap around each of the vias in the substrate and the first adhesive layer, and a second adhesive layer on the second surface of the substrate. The thermal diffusion metal pattern is not to be electrically connected to a semiconductor device to be mounted. The second adhesive layer fills in the gap around each of the vias within the substrate and the first adhesive layer. The gap includes a first gap and a second gap in the substrate and the first adhesive layer, respectively. The second gap is greater in lateral size than the first gap.


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