The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2017

Filed:

Jul. 28, 2016
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Jialei Liu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/823864 (2013.01); H01L 27/092 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method for forming a semiconductor device includes providing a semiconductor substrate including a PMOS region and an NMOS region. A spacer material layer is deposited. Then, a first photo masking and etch process is used to form first sidewall spacers on the sidewalls of the gate structures in the NMOS region. A sacrificial surface layer is formed. Next, a second photo masking and etch process is used to form second sidewall spacers on the sidewalls of the gate structures in the PMOS region. After the second photoresist layer is removed, with the sacrificial layer masking the NMOS region, stress layers are formed in source/drain regions in the PMOS region, and a cover layer is formed on the stress layers. The method further includes removing the sacrificial material layer, the first sidewall spacers, and the second sidewall spacer.


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