The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2017
Filed:
May. 18, 2015
Synopsys, Inc., Mountain View, CA (US);
Ludovic Marc Larzul, Folsom, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A host system receives a description of a design under test (DUT) that includes multiple IP units and is to be emulated by an emulator. The host system compiles the description of the DUT, which includes synthesizing the description, partitioning the DUT, and mapping the partitions to FPGAs included in the emulator that will emulate the DUT. Each IP unit is part of a single partition or partitioned into multiple partitions and mapped to a different set of FPGAs. The host system identifies connections in the DUT between IP units. The host system designates one or more FPGAs of the emulator that have not been allocated to emulate IP units as interface FPGAs. The host system determines a route for each of the identified connections through one of the interface FPGAs. The connections are routed so that there are no direct connections between the sets of FPGAs of two IP units.