The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Sep. 28, 2012
Applicants:

David J. Llapitan, Tacoma, WA (US);

Neal E. Ulen, Yelm, WA (US);

Jeffory L. Smalley, East Olympia, WA (US);

Inventors:

David J. Llapitan, Tacoma, WA (US);

Neal E. Ulen, Yelm, WA (US);

Jeffory L. Smalley, East Olympia, WA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01); H05K 7/10 (2006.01);
U.S. Cl.
CPC ...
H05K 3/301 (2013.01); H05K 7/1007 (2013.01); H05K 7/1061 (2013.01); H05K 2201/10325 (2013.01); H05K 2201/2018 (2013.01); H05K 2203/167 (2013.01);
Abstract

In one embodiment, a load frame and an integrated circuit device are aligned, with a base frame carried on a substrate, along a first alignment axis defined by a first alignment post extending from the base frame to the load frame, in a direction transverse to the substrate, and a first biasing device carried on the base frame is actuated to engage and bias the load frame toward the base frame aligned with the load frame, and to bias the integrated circuit toward the substrate. A latch latches the load and base frames together, aligned with and biased towards each other with the integrated circuit device and the substrate aligned with, and biased toward each other. Other aspects and features are also described.


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