The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Feb. 12, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chia-Hsin Hu, Changhua, TW;

Sun-Jay Chang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/36 (2006.01); H01L 27/088 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 27/0886 (2013.01); H01L 29/1041 (2013.01); H01L 29/36 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 29/7842 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01);
Abstract

A fin field effect transistor (FinFET) and a method of forming the same are introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. A part of the substrate is doped and a region of high dopant concentration and a region of low dopant concentration are formed. Gate stacks are formed, portions of the fins are removed and source/drain regions are epitaxially grown in the regions of high/low dopant concentration. Contacts are formed to provide electrical contacts to source/gate/drain regions.


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