The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

May. 15, 2015
Applicants:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

National Taiwan University, Taipei, TW;

Inventors:

Jhih-Yang Yan, Taipei, TW;

Chee-Wee Liu, Taipei, TW;

Der-Chuan Lai, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/07 (2006.01); H01L 29/78 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0711 (2013.01); H01L 28/55 (2013.01); H01L 29/78 (2013.01);
Abstract

This disclosure provides a negative capacitance gate stack structure with a variable positive capacitor to implement a hysteresis free negative capacitance field effect transistors (NCFETs) with improved voltage gain. The gate stack structure provides an effective ferroelectric negative capacitor by using the combination of a ferroelectric negative capacitor and the variable positive capacitor with semiconductor material (such as polysilicon), resulting in the effective ferroelectric negative capacitor's being varied with an applied gate voltage. Our simulation results show that the NCFET with the variable positive capacitor can achieve not only a non-hysteretic I-Vcurve but also a better sub-threshold slope.


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