The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Jun. 26, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David J. Pelster, Longmont, CO (US);

Yogesh B. Wakchaure, Folsom, CA (US);

Xin Guo, San Jose, CA (US);

Paul D. Ruby, Folsom, CA (US);

Justin R. Dayacap, Folsom, CA (US);

Joseph F. Doller, El Dorado Hills, CA (US);

Robert E. Frickey, Sacramento, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/3445 (2013.01);
Abstract

Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.


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