The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Dec. 22, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Shaul Oron, Petach-Tikva, IL;

Gilad Michael, Tzur Yizhak, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/53 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01); G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/3004 (2013.01); G06F 9/3017 (2013.01); G06F 9/30036 (2013.01); G06F 9/3822 (2013.01); G06F 9/3851 (2013.01); G06F 9/3855 (2013.01); G06F 9/3877 (2013.01); G06F 9/3887 (2013.01); G06F 9/455 (2013.01); G06F 9/4552 (2013.01);
Abstract

A processor includes a front end including a decoder, an execution unit including a shift-sum multiplier (SSM), and a retirement unit. The decoder includes logic identify a multiplication instruction to multiply a first number and a second number. The execution unit includes logic to, based on the instruction, access a look-up table based on the second number to determine a plurality of shift parameters and one or more flag parameters. The SSM includes logic to use the shift parameters to shift the first number to determine a plurality of partial products, and the flag parameters to determine signs of the partial products. The SSM also includes logic to sum the partial products to yield a result of the multiplication instruction.


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